Certain nonvolatile memories, such as a synchronous flash memory, that support “burst” data have a sense circuit that senses all data within a maximum non-continuous burst length at one time and places the data in an output buffer. On such devices, once an address is supplied to the device, it will wait for some initial latency count while all burst data starting from the initial address is sensed and transferred to the output buffer. The data is then output one unit per clock cycle until all sensed data is transferred to the requester.
In cases where the burst length requested by a memory controller is half of the sense width of the memory, half of the sensed data is not used by the controller. Even with address pipelining, if the initial latency count is more than the burst length, there are wasted bus cycles. Thus, there is a need for alternate ways to retrieve information from memory.